A conventional p-channel MOSFET (PFET) may include composite semiconductor source/drain regions with an embedded silicon germanium (SiGe) region on a silicon-on-insulator (SOI) layer. The SiGe region may cause a stress in the SOI layer that improves PFET performance. However, in the conventional PFET, such composite semiconductor source/drain regions have the same thickness as a gate channel region therebetween. Since thinner gate channel region SOI is sought in order to enable improved device characteristics, the thickness of the composite source/drain regions may be constrained to small values. However, manufacturing control issues limit a minimum thickness of the SOI layer in the source/drain regions. Therefore, the thickness of the embedded SiGe region of the conventional PFET is reduced. Consequently, a strain caused by such a SiGe region in the gate channel region of the SOI layer is reduced, which adversely affects performance of such conventional PFET. Accordingly, improved PFETs and methods of manufacturing the same are desired.